As technology nodes continue to advance and decrease in size, they provide continuously less space for contacting on source and drain regions. Resistive losses become a principle challenge in complementary metal-oxide semiconductor (CMOS) transistor performance. That is, as more and more transistors are provided on smaller surfaces, the resistance increases. With conventional techniques, ion implantation into a Si substrate is performed followed by deposition of a metal layer, and then a thermal annealing of the metal and Si substrate to form a metal silicide. However, resistance losses remain a challenge and additional approaches are needed. The main challenge relates to a reduction of available space for making a metal-semiconductor contact and therefore new methods are needed to lower the contact resistance.
A need therefore exists for methodology enabling formation of a low resistive metal-Si contact and resulting devices with improved transistor performance such as on-state current.